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| 5X7 mm SMD, 2.5V, LVDS Frequency Range: Temperature Range: Storage: Input Voltage: Control Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Pulling Range: Linearity: Logic: Terminated 100ohms Temp. 0C to 70C 50MHz to 200MHz 0C to 70C CVLD-025 Model ee Fr ad HS t Le o an R pli m Co Differential LVDS Voltage Controlled Clock Oscillator Designed to meet today's requirements for 2.5V Differential LVDS applications. The CVLD-025 provides very low phase noise & jitter for demanding applications. Available on 16mm tape and reel in quantities of 1,000pcs.. -45C to 90C 2.5V 0.125V 1.25V 1.25V 50mA Typ, 80mA Max Differential LVDS 40/60% Max @ 50% Vdd 1ns Max 50ppm APR Min. (std) 10% Max (Offset 1.25V Typ.) "0" = 1.10 Typical "1" = 1.43 Typical 0.5psec Typ., 1psec RMS Max Jitter: Aging: 12KHz to 20MHz <5ppm 1st/yr, <2ppm every year thereafter Dimensions inches (mm) All dimensions are Max unless otherwise specified. .283 (7.20) SUGGESTED PAD LAYOUT .055 .003 (1.40 .08) #1 #2 #5 #3 #4 .040 .003 (1.0 .08) .148 (3.75) .071 SQ (1.80) P/N Freq DC Denotes pad 1 .203 (5.15) .079 (2.0) #6 .200 .005 (5.08 .13) Bottom View .200 (5.08) Bypass Capacitor Recommended RECOMMENDED REFLOW SOLDERING PROFILE TEMPERATURE 260C 217C 200C 150C Ramp-Up 3C/Sec Max. Critical Temperature Zone Ramp-Down 6C/Sec. Crystek Part Number Guide CVLD-025 - 50 - 155.520 #1 #2 #3 #4 #5 Pulling (APR) Min. #1 Crystek 5x7 SMD PECL VCXO #2 Model 025 = 2.5V #3 Temp. Range: Blank = 0/70C #4 Pulling: (see Table 1) #5 Frequency in MHz: 3 or 6 decimal places Blank 50 (std) 100ppm 50ppm Preheat 180 Secs. Max. 8 Minutes Max. 90 Secs. Max. Table 1 260C for 10 Secs. Max. Example: CVLD-025-50-155.520 = 2.5V, 40.60, 0/70C, 50ppm APR, 155.520 MHz NOTE: Reflow Profile with 240C peak also acceptable. Pad 1 2 3 4 5 6 Connection Volt Cont. E/D GND OUT COUT Vdd Enable/Disable Function E/D pin Open "1" level 2.2V Min "0" level 0.4V Max Output pin Active Active High Z Specifications subject to change without notice. TD-070301 Rev.A |
Price & Availability of CVLD-025
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